Direct digital synthesizers, commonly referred to as DDS or DDFS, are widely used in digital devices. A direct digital frequency synthesizer (DDS) can be considered a special case of a digital mixer. While the mixer rotates an arbitrary point in the plane by an angle specified by the normalized rotation angle, θ, the DDS always rotates a fixed point, which can be considered to be the point (1, 0).
The phase accumulator in a DDS employs a relatively long phase word (e.g., the word length M=32 bits for the examples we have been using here, and M=48 bits has been used in commercial products described in “1 GSPS Direct Digital Synthesizer with 14-Bit DAC,” AD9912 Data Sheet, Analog Devices, Inc., 2007-2010 and “2.7 GHz DDS-Based AgileRF™ Synthesizer,” AD9956 Data Sheet, Analog Devices, Inc., 2004). When incrementing the phase accumulator by adding a frequency control word (FCW) to it, a long carry-ripple delay can be problematic. For example, the use of Artisan library cells for TSMC 0.18-μm CMOS can require a carry-ripple delay that is sufficiently long as to make running the phase accumulator at a desired 250-MHz speed expensive in terms of power dissipation. A well-known technique for increasing the frequency at which a DDS phase accumulator can be updated is to employ some form of pipelining of the phase accumulator.
When pipelined, a 32-bit phase accumulator can run at 250-MHz in TSMC 0.18-μm CMOS. In addition to the increased hardware expense incurred by the pipelining circuitry, one residual problem remains: the inherent pipeline-induced delay and/or complexity when one desires to instantaneously change the frequency being generated by changing FCW. (Instantaneous frequency changing is one of the very desirable capabilities of a DDS; indeed, such a feature is perhaps unique to a DDS, in comparison with other types of oscillators.) When changing to a new FCW value, in a pipelined-phase-accumulator system, it can be a problem that the least-significant part of the phase accumulator must be incremented in a previous output-data cycle to that in which the most-significant part of the phase accumulator is incremented, and solving this and related problems can require additional and more complicated circuitry and/or performance compromises.
What is therefore needed is a DDS that solves the phase accumulator speed-up problem.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers can indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.